Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■SCSI interface
Target: Built-in SCSI HDD, PC-9801-55･U･L, PC-9801-92
PC-9801FA-03, PC-9821A-E10, PC-9821N-U05
PC-H98-B03
PC-H98-B12 compatible mode
Explanation The PC-9800 series uses the Western Digital WD33C93 series as a
SCSI controller. The relationship with the chips used on each board is as
follows. The WD33C93B allows synchronous transfer.
----------------+------------------------------
Chip | Board
----------------+------------------------------
WD33C93 | PC-9801-55
----------------+------------------------------
WD33C93A | PC-9801-55U･L
| PC-9801FA-03,PC-H98-B03
| Built-in SCSI interface
----------------+------------------------------
WD33C93B | PC-9821-92,PC-9821A-E10,
| PC-H98-B12,PC-9821N-U05
----------------+------------------------------
* The SCSI interface board built into the PC-9821Af etc. is equivalent to the PC-9821A-E10.
u Synchronous transfers are possible with the SCSI interface using the WD33C93B.
o When the PC-H98-B12 is set to extended mode, it does not use the DMA in the
main unit, but instead performs bus master transfers using the external DMA on
the board. In extended mode, the WD33C93 registers are directly mapped to the
CPU's I/O space without using two-stage I/O.
o When performing bus master transfers, a VDS-compliant virtual 86 manager
must be used. If VDS is installed, the BIOS uses VDS functions to obtain the
physical address.
o The PC-9801-92, PC-9821A-E10, and PC-9821N-U05 can use a CPU data transfer
mode that uses FIFO.
Related 0000:0460-0000:047Fh
0000:0482h
0000:0483h
0000:0484h bit 7-5
0000:05A5h
0000:05ADh bit 5
0000:05AFh
INT 4Bh
I/O 0CC0h,0CD0h,0CE0h,0CF0h
Name Register address set
Auxiliary status
Target PC-9801-55 first generation/U/L, PC-H98-B03
PC-9801FA-03, PC-9821A-E10, PC-9821N-U05
PC-H98-B12 compatible mode
Chip WD33C93
Function
[READ] Auxiliary status
bit 7: INT
1 = Interrupt has occurred
0 = No interrupt has occurred
bit 6: LastCommandIgnored
bit 5: ChipBusy
bit 4: CommandInProgress
bit 3,2: 00b
bit 1: ParityError
1 = Parity error
0 = No parity error
bit 0: DBR
1 = Valid data present
0 = No valid data present
[WRITE]
bit 7-0: AR
* Address of control register
Description o Sets the address of the register to be read/written with I/O 0CC2h.
o Refers to auxiliary status.
Related I/O 0CC2h
I/O 0CC2h,0CD2h,0CE2h,0CF2h
Name Control register
Target PC-9801-55 first generation, U, L
PC-9801FA-03
PC-9821A-E10
PC-9821N-U05
PC-H98-B03
PC-H98-B12 compatible mode
Chip WD33C93
Function
[READ/WRITE] Get/set control register
---------+-------+----------------------------------------------
AR value | R/W |
---------+-------+----------------------------------------------
00h | R/W | Own ID
| | bit 7,6: FS0,FS1■[WD33C93B]
| | 11b = Undefined
| | 10b = Division ratio 4 (16-20MHz)
| | 01b = Division ratio 3 (12-15MHz)
| | 00b = Division ratio 2 (8-10MHz)
| | bit 5: Reserved
| | bit 4: EnableHostParity
| | bit 3: AdvancedFeatures
| | bit 2-0: ID2-ID0
| | 000b = SCSI ID0
| | 001b = SCSI ID1
| | 010b = SCSI ID2
| | 011b = SCSI ID3
| | 100b = SCSI ID4
| | 101b = SCSI ID5
| | 110b = SCSI ID6
| | 111b = SCSI ID7
| | * Set the ID number of the interface board
---------+-------+----------------------------------------------
01h | R/W | Control
| | bit 7-5: DmaModeSelect
| | 000b = DMA_POLLED
| | 001b = DMA_BURST
| | 010b = DMA_WD_BUS
| | 100b = DMA_NORMAL
| | bit 4: HaltOnHostParity
| | bit 3: EndingDisconnectInt
| | bit 2: IntermediateDisconnectInt
| | bit 1: HaltOnAtn
| | bit 0: HaltOnParity
---------+-------+----------------------------------------------
02h | R/W | Time out Period
| | * Set the time until timeout
---------+-------+----------------------------------------------
03h | R/W | Total Sectors /CDB1
---------+-------+----------------------------------------------
04h | R/W | Total Head /CDB2
---------+-------+----------------------------------------------
05h | R/W | Total Cylinders(MSB) /CDB3
---------+-------+----------------------------------------------
06h | R/W | Total Cylinders(LSB) /CDB4
---------+-------+----------------------------------------------
07h | R/W | Logical Address(MSB) /CDB5
---------+-------+----------------------------------------------
08h | R/W | Logical Address /CDB6
---------+-------+----------------------------------------------
09h | R/W | Logical Address /CDB7
---------+-------+----------------------------------------------
0Ah | R/W | Logical Address(LSB) /CDB8
---------+-------+----------------------------------------------
0Bh | R/W | Sector Number /CDB9
---------+-------+----------------------------------------------
0Ch | R/W | Head Number /CDB10
---------+-------+----------------------------------------------
0Dh | R/W | Cylinder Number(MSB) /CDB11
---------+-------+----------------------------------------------
0Eh | R/W | Cylinder Number(LSB) /CDB12
---------+-------+----------------------------------------------
0Fh | R/W | Target LUN
| | bit 7: TargetLunValid
| | bit 6: DisconnectOk
| | bit 5～3: Reserved (always 000b)
| | bit 2～0: TL2～TL0
---------+-------+----------------------------------------------
10h | R/W | Command Phase
| | bit 7: undefined (set to 0)
| | bit 6～0: CP6～CP0
| | 00h = NO_SELECT
| | 10h = SELECTED
| | 20h = IDENTIFY_SENT
| | 30h = COMMAND_OUT
| | 41h = SAVE_DATA_RECEIVED
| | 42h = DISCONNECT_RECEIVED
| | 43h = LEGAL_DISCONNECT
| | 44h = RESELECTED
| | 45h = IDENTIFY_RECEIVED
| | 46h = DATA_TRANSFER_DONE
| | 47h = STATUS_STARTED
| | 50h = STATUS_RECEIVED
| | 60h = COMPLETE_RECEIVED
---------+-------+----------------------------------------------
11h | R/W | Synchronous Transfer
| | bit 7: Reserved (set to 0)
| | bit 6-4: TP2-TP0
| | bit 3-0: OF3 to OF0
---------+-------+----------------------------------------------
12h | R/W | Transfer Count(MSB)
---------+-------+----------------------------------------------
13h | R/W | Transfer Count
---------+-------+----------------------------------------------
14h | R/W | Transfer Count(LSB)
---------+-------+----------------------------------------------
15h | R/W | Destination ID
| | bit 7: SelectCommandChain
| | bit 6: DataDirection
| | bit 5-3: Reserved (always 000b)
| | bit 2-0: DI2~DI0
---------+-------+----------------------------------------------
16h | R/W | Source ID
| | bit 7: EnableReselection
| | bit 6: EnableSelection
| | bit 5: DisableParitySelect
| | bit 4: Reserved
| | bit 3: TargetIdValid
| | bit 2～0: SI2～SI0
---------+-------+----------------------------------------------
17h | READ | SCSI Status
| | bit 7: ServiceRequired
| | bit 6: Terminated
| | bit 5: AbortedPaused
| | bit 4: CommandComplete
| | bit 3: PhaseStateValid
| | bit 2-0: PhaseState
| | 00h = Reset by command or MR input
| | 10h = Reselect command completed successfully
| | 11h = Select command completed successfully
| | 13h = Receive, Send, Reselect and Trasfer,
| | Wait for Receive command completed successfully (no ATN)
| | 14h = Receive, Send, Reselect and Trasfer,
| | Wait for Receive command completed successfully (ATN)
| | 16h = Select and Transfer command completed successfully
| | 18h = Transfer command completed successfully (data out phase)
| | 19h = Transfer command completed successfully (data phase)
| | 1Ah = Transfer command completed successfully (command phase)
| | 1Bh = Transfer command completed successfully (status phase)
| | 1Ch = Transfer command completed successfully
| | (Unspecified information out phase)
| | 1Dh = Transfer command completed successfully
| | (Unspecified information in phase)
| | 1Eh = Transfer command completed successfully (message out phase)
| | 1Fh = Transfer command completed successfully (message in phase)
| | 20h = Transfer command (message in phase)
| | Pause with ACK asserted
| | 21h = During Select and Transfer command
| | Received Save Data Pointer message
| | 22h = Select, Reselect command aborted
| | 23h = Receive, Send command halted or
| | aborted (no ATN)
| | 24h = Receive, Send command halted or
| | aborted (with ATN)
| | 28h = Transfer command aborted (data out phase)
| | 29h = Transfer command aborted (data in phase)
| | 2Ah = Transfer command aborted (command phase)
| | 2Bh = Transfer command aborted (status phase)
| | 2Ch = Transfer command was aborted
| | (Unspecified information out phase)
| | 2Dh = Transfer command was aborted
| | (Unspecified information in phase)
| | 2Eh = Transfer command was aborted
| | (Message out phase)
| | 2Fh = Transfer command was aborted (Message in phase)
| | 40h = Invalid command was aborted
| | 41h = Command was terminated and disconnected
| | 42h = Select, Reselect command was in progress
| | Timeout
| | 43h = Parity error and command was aborted
| | Terminated (no ATN)
| | 44h = Parity error and command was
| | Terminated (with ATN)
| | 46h = Incorrect target device
| | Reselected
| | 47h = Received message, status,
| | Incorrect command
| | 48h = Unexpected information phase request (data out phase)
| | 49h = Unexpected information phase request (data in phase)
| | 4Ah = Unexpected information phase request (command phase)
| | 4Bh = Unexpected information phase request (status phase)
| | 4Ch = Unexpected information phase request
| | (Unspecified information out phase)
| | 4Dh = Unexpected information phase request
| | (Unspecified information in phase)
| | 4Eh = Unexpected information phase request
| | (Message out phase)
| | 4Fh = Unexpected information phase request (Message in phase)
| | 80h = Reselected
| | 82h = Selected (no ATN)
| | 83h = Selected (ATN present)
| | 84h = ATN signal already asserted
| | 85h = Disconnection occurred
| | 88h = REQ asserted following connection
| | (Data out phase)
| | 89h = REQ asserted following connection
| | (Data in phase)
| | 8Ah = REQ asserted following connection
| | (Command phase)
| | 8Bh = REQ asserted following connection
| | (Status phase)
| | 8Ch = REQ asserted following connection
| | (Unspecified information outphase)
| | 8Dh = REQ is asserted following a connection
| | (Unspecified information inphase)
| | 8Eh = REQ is asserted following a connection
| | (Message outphase)
| | 8Fh = REQ is asserted following a connection
| | (Message inphase)
---------+-------+----------------------------------------------
18h | R/W | Command
| | 00h = Reset
| | 01h = Abort
| | 02h = Assert ATN
| | 03h = Negate ATN
| | 04h = Disconnect
| | 05h = Reselect
| | 06h = Select With ATN
| | 07h = Select Without ATN
| | 08h = Select With ATN and Transfer
| | 09h = Select Without ATN and Transfer
| | 0Ah = Reselect and Receive Data
| | 0Bh = Reselect and Send Data
| | 0Ch = Wait For Select and Receive
| | 0Dh = Send Status and Command Complete
| | 0Eh = Send Disconnect Message
| | 0Fh = Set Disconnect Interruput
| | 10h = Receive Command
| | 11h = Receive Data
| | 12h = Receive Message Out
| | 13h = Receive Unspecified Info Out
| | 14h = Send Status
| | 15h = Send Data
| | 16h = Send Message In
| | 17h = Send Unspecified Info IN
| | 18h = Translate Address
| | 20h = Transfer Info
| | 21h = Transfer Pad
---------+-------+----------------------------------------------
19h | R/W | Data
---------+-------+----------------------------------------------
1Ah | R/W | AuxiliaryStatus
---------+-------+----------------------------------------------
30h | R/W | Memory Bank
| | bit 7: ROM1
| | bit 6: ROM0
| | 1 = upper ROM bank
| | 0 = lower ROM bank
| | * Set ROM bank
| | bit 5,4: Unused (set to 00b)
| | bit 3: MEM1
| | 1 = Local memory access permitted from the system side
| | 0 = Local memory access prohibited from the system side
| | bit 2: IRE1
| | 1 = Interrupts permitted from the interface to the system side
| | 0 = Interrupts prohibited from the interface to the system side
| | bit 1: WRS1
| | 1 = RST signal on the SCSI bus is active LOW
| | 0 = Bus reset from the interface board is released
| | bit 0: 0
---------+-------+----------------------------------------------
31h | READ | Memory Window
| | bit 7: Unused (set to 0)
| | bit 6,5: HST1,HST0
| | 11b = CPU 286,386,486
| | 10b = 98XL,XL^2,RL
| | 01b = V30
| | 00b = 98XA
| | * Device type setting
| | bit 4-3: WND4,WND3
| | 00b = E8000-E8FFFh
| | 01b = EA000-EAFFFh
| | 10b = EC000-ECFFFh
| | 11b = EE000-EEFFFh
| | * Memory window setting in high-resolution mode
| | bit 2-0: WND2-WND0
| | 000b = D0000-D0FFFh
| | 001b = D2000-D2FFFh
| | 010b = D4000-D4FFFh
| | 011b = D6000-D6FFFh
| | 100b = D8000-D8FFFh
| | 101b = DA000-DAFFFh
| | 110b = DC000-DCFFFh
| | 111b = DE000-DEFFFh
| | * Memory window settings in normal mode
| | * Reads the dip switch settings on the interface board
---------+-------+----------------------------------------------
32h | R/W | PkgIdRegister (NEC reserved)
| | FDh = External SCSI interface board
| | FEh = Built-in SCSI interface board or
| | Internal SCSI HDD interface
---------+-------+----------------------------------------------
33h | READ | RESET/INT
| | bit 7: RRST
| | 1 = RST signal on SCSI bus is active LOW for 25μS or more (becomes 0 when read)
| | 0 = RST signal on SCSI bus is inactive
| | * SCSI bus reset pin status
| | bit 6: Unused
| | bit 5-3: ILV2-ILV0
| | 000b = INT0
| | 001b = INT1
| | 010b = INT2
| | 011b = INT3
| | 100b = INT5
| | 101b = INT6
| | * DIP switch interrupt level setting can be read
| | bit 2-0: ID2-ID0
| | 000b = ID0
| | 001b = ID1
| | 010b = ID2
| | 011b = ID3
| | 100b = ID4
| | 101b = ID5
| | 110b = ID6
| | 111b = ID7
| | * Reads the SCSI ID setting of the DIP switch
---------+-------+----------------------------------------------
33h | WRITE | Prohibited (NEC reserved)
---------+-------+----------------------------------------------
34h | R/W | FifoIntGuard (NEC reserved)
| | bit 7: SET
| | bit 6: WDS
| | bit 5: OR1
| | bit 4: FLI
| | bit 3: WDI
| | bit 2: FULL
| | bit 1: EMPTY
| | bit 0: BC1
---------+-------+----------------------------------------------
35h | WRITE | FifoAdjust (NEC reserved)
| | bit 7,6: FIFO transfer mode
| | 11b = Setting prohibited
| | 10b = FIFO operation start
| | 01b = FIFO stop
| | 00b = Setting prohibited
| | bit 5: CW1 (FIFO transfer direction)
| | 1 = CPU → FIFO
| | 0 = FIFO → CPU
| | bit 4: FSW
| | bit 3: CSW
| | bit 2-0: Reserved (always 000b)
---------+-------+----------------------------------------------
* Reads and writes the contents of the register set by I/O 0CC0h (AR)
Explanation o Performs two-stage I/O operations in pairs with I/O 0CC0h.
Sets/gets the contents of the WD33C93 register.
Related I/O 0CC0h
I/O 0CC4h,0CD4h,0CE4h,0CF4h
Name Status,Interrupt control
Chip WD33C93 peripheral
Function
[READ] Status read
bit 7: Unused
bit 6: TCI Interrupt by DMATCO signal
1 = Interrupt occurred
0 = No interrupt
bit 5-2: Unused
bit 1,0: DMA1,DMA0 Switch status of DMA channel to be used
[WRITE] Command write
bit 7-5: 000b
bit 4: TCIR
* Reset TC interrupt
bit 3: TCMR
* Reset TC interrupt mask
bit 2: TCMS
* Set TC interrupt mask
bit 1: DMER
* Reset DMA enable
bit 0: DMES
* Set DMA enable
Explanation o Reads the status of WD33C93.
o Controls interrupts.
Related I/O 0CC0h,0CC2h
I/O 0CD0h,0CD2h
I/O 0CE0h,0CE2h
I/O 0CF0h,0CF2h
I/O 0C84h
Name FIFO control/status acquisition
Undocumented
Target PC-9801-92,PC-9821A-E10,PC-9821N-U05
Chip WD33C93 peripheral
Function
[READ/WRITE]
bit 15-0: Number of data in FIFO (unit is bytes)
Explanation o Controls input and output of FIFO.
o FIFO size is 8000h bytes.
Related I/O 1C84h
I/O 1C84h
Name FIFO data input/output
Undocumetned
Target PC-9801-92, PC-9821A-E10, PC-9821N-U05
Chip WD33C93 peripheral
Function
[READ/WRITE]
bit 31-0: FIFO data input/output
Explanation o Performs FIFO data input/output.
o Byte and word access are possible.
Related I/O 0C84h
I/O 0nm0-3nmEh,4nm2h
Name SCSI chip control [DATA]
Undocumented
Target PC-H98-B12
Chip WD33C93
Function
[READ/WRITE]
* SCSI chip control [DATA]
------------+-------
I/O address | AR
------------+-------
0nm0h | 00h
0nm2h | 01h
0nm4h | 02h
0nm6h | 03h
0nm8h | 04h
0nmAh | 05h
0nmCh | 06h
0nmEh | 07h
1nm0h | 08h
1nm2h | 09h
1nm4h | 0Ah
1nm6h | 0Bh
1nm8h | 0Ch
1nmAh | 0Dh
1nmCh | 0Eh
1nmEh | 0Fh
2nm0h | 10h
2nm2h | 11h
2nm4h | 12h
2nm6h | 13h
2nm8h | 14h
2nmAh | 15h
2nmCh | 16h
2nmEh | 17h
3nm0h | 18h
3nm2h | 19h
3nm4h | 1Ah
3nm6h | 1Bh
3nm8h | 1Ch
3nmAh | 1Dh
3nmCh | 1Eh
3nmEh | 1Fh
4nm2h | 30h
------------+-------
* The WD33C93 registers are basically mapped as follows:
CPU I/O address 00xx mmmm nnnn yyyy
mmmm,nnnn follow NESA's \ |
I/O allocation rules. \ |
\ |
\ |
\ |
WD33C93 register address 00xx yyyy
Explanation o Accesses each register of WD33C93.
o In extended mode, each register of WD33C93 is directly mapped onto the CPU's
I/O space, not two-level I/O.
Related I/O 8nmEh bit 6
I/O 4nm0h
Name Status, interrupt control
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[READ/WRITE]
* Same as I/O 0CC4h
Explanation o In extended mode, use I/O 4nm0h instead of I/O 0CC4h.
Related I/O 8nmEh bit 6
I/O 5nm0h
Name DMA transfer size (bits 7-0)
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
bits 7-0: DMA transfer length bits 7-0
Explanation o Sets the DMA transfer length bits 7-0.
o The unit is bytes.
Related I/O 8nmEh bit 6
I/O 5nm1h,5nm2h
I/O 5nm1h
Name DMA transfer size (bits 15-8)
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
Bits 7-0: DMA transfer length bits 15-8
Explanation o Sets bits 15-8 of the DMA transfer length.
o The unit is bytes.
Related I/O 8nmEh bit 6
I/O 5nm0h,5nm2h
I/O 5nm2h
Name DMA transfer size bits 23-16
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
Bits 7-0: DMA transfer length bits 23-16
Explanation o Sets bits 23-16 of the DMA transfer length.
o The unit is bytes.
Related I/O 8nmEh bit 6
I/O 5nm0h,5nm1h
I/O 5nm4h
Name DMA transfer address bits 7-0
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
bits 7-0: DMA transfer address bits 7-0
Explanation o Sets bits 7-0 of the DMA transfer address.
Related 0000:05ADh bit 5
I/O 8nmEh bit 6
I/O 5nm5h,5nm6h,5nm7h
I/O 5nm5h
Name DMA transfer address bits 15-8
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
bits 7-0: DMA transfer address bits 15-8
Explanation o Sets bits 15-8 of the DMA transfer address.
Related 0000:05ADh bit 5
I/O 8nmEh bit 6
I/O 5nm4h,5nm6h,5nm7h
I/O 5nm6h
Name DMA transfer address bits 23-16
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
Bits 7-0: DMA transfer address bits 23-16
Explanation o Sets bits 23-16 of the DMA transfer address.
Related 0000:05ADh bit 5
I/O 8nmEh bit 6
I/O 5nm4h,5nm5h,5nm7h
I/O 5nm7h
Name DMA transfer address bits 31-24
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
bit 7-0: DMA transfer address bits 31-24
Explanation o Sets bits 31-24 of the DMA transfer address.
Related 0000:05ADh bit 5
I/O 8nmEh bit 6
I/O 5nm4h,5nm5h,5nm6h
I/O 5nm8h
Name External DMA control
Undocumented
Target PC-H98-B12
Chip WD33C93 peripheral
Function
[WRITE]
bit 7: DMA control
1 = Stop DMA
0 = Start DMA
bit 6-2: Unused
bit 1,0: Transfer direction
11b = Setting prohibited
10b = Read (memory to I/O)
01b = Write (I/O to memory)
00b = Verify (I/O read)
Explanation o Controls external bus master DMA.
Related I/O 8nmEh bit 6
I/O 8nmEh
Name NESA-FO register 0Eh
Target PC-H98-B12
Chip NESA-FO
Function
[READ]
bit 6: Compatible mode/Extended mode
1 = Compatible mode
0 = Extended mode
Explanation o Sets the mode of the PC-H98-B12 board.
o When in Extended mode, the I/O ports I/O 0nm0-3nmEh, 4nm0h, 4nm2h,
5nm0-5nm8h are used, and the WD33C93 registers are accessed by direct I/O
operations by the CPU.
Related I/O 0nm0-3nmEh, 4nm2h
I/O 4nm0h
I/O 5nm0-5nm8h